1. Field of the Invention
The present invention relates to a memory device storing information and, more particularly, to a ferroelectric memory device using a ferroelectric material as a dielectric film in a capacitor.
2. Description of Prior Art
Generally, a nonvolatile ferroelectric random access memory (NVFRAM), based on one-transistor and one-capacitor memory cell, has characteristics of fast access time and a small chip size. These characteristics result from a ferroelecric material used in the capacitor of the memory cell. FIG. 1 shows a symbol of a ferroelectric capacitor and the hysteresis loop thereof. That is, the polarization charge Q to voltage applied to the capacitor is shown in FIG. 1. In the ferroelectric capacitor, even if the voltage difference between two terminals of the capacitor is zero voltage, the charge Q may be one of two values of P1 and P2, and thus storing a binary data. Accordingly, based on these characteristics, the ferroelectric capacitor has been used in the nonvolatile memory device.
According to the variation of voltage applied to the both terminals of the ferroelectric capacitor, the stored charges therein vary with the degree of polarization of the ferroelectric material as shown in the hysteresis loop of FIG. 1. For example, when a large negative voltage of less than -3 V is applied to the capacitor having the polarization charge of P1, the polarization charges may reach P3 along the hysteresis loop. When the applied voltage is removed and then the voltage applied to the ferroelectric capacitor is zero voltage, the polarization charge may reach P2 again. That is, the polarization charges may vary along an arrow in the hysteresis loop in response to the applied voltage and the data is detected by the charges induced in the ferroelectric capacitor.
When the word line is activated during reading out the data stored in the ferroelectric memory, the potential on the bit line is in one of low or high voltage level, for example, V0 or V1, according to the stored data (logic "0" or "1"). Since the voltage levels of V0 and V1 are small signals, the voltage difference between these voltage levels should be amplified by a sense amplifier in similar to DRAM devices. Accordingly, to discriminate the low and high voltage level, it is required to provide an intermediate voltage level, i.e., a reference voltage level, to a bit bar line. By determining whether the voltage applied to the bit line is lower or higher than the reference voltage, the logic data "0" or "1" is determined.
FIG. 2 is a circuit diagram illustrating a conventional NVFRAM. In FIG. 2, reference numerals R1, M1, BL, /BL and S1 denote a reference voltage generator, a memory cell array for data storage, a bit line, a bit bar line and a sense amplifier, respectively. Reference cells C1 and C2 in the reference voltage generator R1 store a logic data "0" or "1" and switching transistors RT1 and RT2 are turned on under the control of the activated word line. After equalizing a reference bit line RBL having a charge .DELTA.Q1, which is induced by a reference cell, with a reference bit bar line /RBL having a charge .DELTA.Q0, which is induced by another reference cell, the equalized reference voltage is transferred to one of the bit line pair through a transfer transistor controlled by a control signal DTGT. It should be noted that the bit line coupled to the reference bit line is not electrically coupled to the ferroelectric cell in the memory array in order to be used as a reference voltage supply means. The one of the bit line pair is used as the reference voltage supply means and the other of the bit line pair is uses as a data path from the ferroelectric capacitor. In similar to DRAMs, the sense amplifier S1 senses the voltage difference between the bit line and the bit bar line.
In this conventional ferroelectric memory device including a plurality of memory arrays, because one reference voltage generator is repeatedly read out for a plurality of bit lines, the reference cells C1 and C2 are frequently used. That is, in case of the scheme in FIG. 2, the reference cells C1 and C2 are used N times as frequently as N memory cells. For example, assuming that 256 memory cells are provided in the memory array, the reference cells C1 and C2 must be read out even if any of 256 memory cells is selected. Based on the characteristics of ferroelectric material, the frequent reading operation causes the reference cells C1 and C2 to be fatigued. In particular, in case of this scheme in FIG. 2, the reference cells C1 and C2 are fatigued 256 times as fast as the ferroelectric capacitors in the memory array. This fatigue in the reference cells C1 and C2 may make the reference voltage incorrect, thereby causing an incorrect data reading operation.